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With combinational logic the output states depend entirely on
the state of the inputs. With sequential logic the output of a logic system
depends not only on the state of the inputs and outputs of the various logic
gates used, but also on the sequence or order in which things occur.
| As an example, look at the latch shown on
the right. It is a simple S - R flip-flop built from NAND gates. The S stands for set and the
R for reset. It should operate as
follows: when set is taken low the output should go high.
When reset is taken low the output should go low again. If
set is taken high or even toggled (switched alternately high and low)
before reset is taken low the output should be unaffected, however before
reset can take the output low, set has to made high again. This will
only happen if the inputs are in the correct state but more importantly
it will only happen if the correct sequence of events occurs. |
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You may find this difficult to follow but
you should see that if reset is 1 the output goes to 1 when set is 0. The output
then remains at 1 no matter what the state of the set
input, showing that the output is 'latched' this is true until reset is taken
to 0 and set is returned to 1. If reset is kept at 0 the output follows
the state of the set input. It will only latch again if reset is taken
back to 1. |
The correct sequence has to be set low - set high - reset
low - reset high and so on....
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The behaviour of a sequential
system, even a relatively simple one such as the S-R flip flop can be
difficult to understand (and even more difficult to describe in words).
For this reason we often draw each input and output in graphical form.
The four graphs on the left show how the states of the inputs and outputs change as
time progresses.
We call this a timing diagram. You will see
that the set input starts at logic 1. As it is taken to logic 0 output Q
rises from logic 0 to logic 1 and Q
falls to logic 0.
The set input must rise to logic 1 before reset is
taken to logic 0, so that Q can fall to logic 0 and Q
can rise to logic 1 ready to begin the sequence again. |
A major problem with the S - R flip flop (or bistable)
is that when Set = 0 and Reset = 0 we find that both Q and Q
= 1. If both S and R are then taken to logic 1 simultaneously it is
impossible to predict whether the flip-flop will return to its set or reset
state. Obviously this ambiguity needs to be avoided and this can be achieved by
changing the inputs alternately as shown above.
In large well designed digital systems it would not be good
practice to allow the sequence
of events to be determined by individual logic gates, as this leads to problems. Ideally
they should all change state at the same time. This is achieved by 'clocking'
the logic system. A clocked logic system is one which responds to a clock pulse.
If the same clock pulse is applied to all bistables at the same time things
happen in an orderly rather than haphazard way.
| As we have seen however a simple S - R bistable does
not act reliably when both inputs change simultaneously, so they are
rarely used in the form we have looked at so far. A clocked S - R
bistable can be made as shown.
A clocked S - R flip-flop prevents S and R being
passed to the flip flop until the clock pulse is taken high. The finite
time between clock pulses allows the outputs to settle before the next
change occurs.
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'Clocks'
The clock pulses are provided by some form of astable
or pulse generator. In large systems it is probably a crystal-controlled
oscillator with a frequency measured in MHz, but for simple systems it
could be any astable which produces fast rise and fall times i.e. one
that produces a good 'square' wave.
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Triggering
Bistables are triggered in two ways. In level
triggering the bistables change state when the logic level is at 1 or 0.
With edge triggering the bistables change state on either the rising
edge or falling edge of the waveform. In general edge triggering is more
satisfactory because the change of state is at a precise moment in time.
With level trigering the change of state can occur at any time the logic
level is at 1 or 0.
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| One way to ensure that the S and R inputs are never
held at the same logic level (to avoid the problems mentioned above) is
to connect the S and R inputs together with an inverter in between. This
ensures that S is always the complement of R and vice-versa. This
arrangement is called a 'D-type' flip flop. It has a single input. The
'D' stands for data. The signal on the data input is transferred to the
Q output, each time the clock goes to logic 1.
D Type Flip-Flop |
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A 'D' Type Flip Flop
J -K Flip Flop |
A 'D' Type flip-flop can be converted to a T - type or
toggling flip-flop by connecting the Q
output to the D input. Successive brief clock pulses will cause the output
to toggle. |
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| J |
K |
Q
after clock pulse |
Q
after clock pulse |
| 0 |
0 |
stays
at 0 or 1 |
stays
at 0 or 1 |
| 0 |
1 |
0 |
1 |
| 1 |
0 |
1 |
0 |
| 1 |
1 |
toggles |
toggles |
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| The symbol on the
right shows a J - K flip flop. This is a very versatile flip-flop which
can be used to build any of the flip-flops already looked at. Its truth
table is shown above. There is no indeterminate state each input
combination will give a definite output state. |
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| If the length of a pulse is greater than the switching
time of a flip-flop it is possible for outputs to 'race' causing
unreliable operation. To prevent this 'race' condition from occurring.
Two flip flops can be used to create what is called a master-slave
arrangement. The way they work is relatively simple. To begin with the
master flip-flop collects the data from the inputs whilst the slave
flip-flop is isolated from the outputs, then the slave flip-flop receives the
data from the master flip-flop and passes it to the output while the
master is isolated from the inputs. |
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Counting Circuits
All counting circuits are based on the binary counter. A four bit
binary counter will have one input bit and four output bits (usually
labelled A, B, C, D). This can be built from four flip-flops connected
in series. |
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| This type of counter
is known as a ripple counter or asynchronous counter, because
there is a delay between the clock pulse arriving and the counter
updating as changes ripple through each flip flop. |
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| The rippling effect is shown in
the timing diagram above. An ideal counter would update all four flip
flops at the same time. The dotted line shows how the ripple effect is
cumulative and the delay can become problematic causing errors in the
next part of the system.
The ripple effect can be remedied with the addition of
two AND gates as shown below. This is known as a four bit synchronous
counter because the clock inputs of all stages are pulsed together to
ensure that they all change simultaneously. The AND gates ensure that
nothing toggles unless all the previous stages are at logic 1. |
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Both the synchronous and asynchronous 4 bit
binary counters will count from 0000 to 1111 a total of 16 clock
pulses.
Unless we want to count in Hexadecimal we
will need to decode these counters to count from 0000 (decimal 0) to 1001
(decimal 9) in order to drive Decimal or Seven Segment outputs.
This is easily done by connecting outputs A
and D to an AND gate and using this to reset the counter (see left). |
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A Binary Counter being decoded
into a decimal (usually called a BCD or binary coded decimal Decade
counter) |
| We frequently want to present the
output of a counter in a form which is more easily recognised.
If for instance we want to display the numbers 0 - 9 we
have to decode the output from a BCD counter to illuminate a display in
the correct sequence to light a seven segment LED ( Light Emitting Diode)
or LCD (Liquid Crystal Display). |
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| The circuit below shows a BCD
counter feeding a seven segment Decoder/Driver |
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